1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to an interconnection structure of a semiconductor device provided with a test element group for measuring the characteristics of a cell transistor of the semiconductor device.
2. Description of the Background Art
As semiconductor devices are developed with higher degrees of integration, increased storage capacity of the semiconductor devices is required while the chip sizes are being reduced. Consequently, the semiconductor device structures are becoming increasingly complex in the recent years.
On the other hand, semiconductor devices in the course of their development are provided with a test element group (hereinafter referred to as a TEG) for evaluating circuits, devices, processes and the like. When providing a cell transistor TEG for evaluating a cell transistor of a semiconductor device, for instance, the electrical contact interconnection is drawn from a storage node provided in the cell transistor.
Due to the increasing complexity of the semiconductor device structures in the recent years noted above, the structures of storage nodes are becoming more complex, and so are the methods of manufacturing them.
Despite the increasing complexities in the structures of the semiconductor devices and the methods of manufacturing them, however, the evaluation of a cell transistor TEG must be performed accurately. Thus, a structure of an interconnection drawn from an electrode of a semiconductor device for providing a cell transistor TEG becomes important.
Prior Art Arrangement
FIG. 23 shows a cross sectional structure of a cell transistor TEG provided for a cell transistor having a conventional thick film stacked capacitor structure. In the structure of this cell transistor TEG, an active region 20 defining a source/drain region and an element isolating oxide film 30 are provided in the prescribed region of the main surface of a silicon substrate 100 which is the semiconductor substrate.
A transfer gate 1B is provided on silicon substrate 100 with a gate insulating film 1A provided therebetween. Transfer gate 1B is covered by a nitride film 1D and a TEOS (Tetra Ethyl Ortho Silicate) film 1C.
A bit line (BL) 2 is connected via a bit line contact plug 4B to one of the active regions 20, and a storage node (SN electrode) 5 is connected via a storage node contact (SC) plug 4S to another of the active regions 20. In addition, transfer gate 1B, nitride film 1D, TEOS film 1C, and bit line (BL) 2 are covered by an interlayer BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) film 3.
On the planarized interlayer BPTEOS film 3, storage node electrode 5 is provided which is formed by depositing doped polysilicon of 500 nm in film thickness, forming a thick film stacked capacitor structure. Storage node electrode 5 is covered by an interlayer contact film 6 formed of a TEOS film.
A contact plug 7 formed of tungsten and aluminum interconnection 8 electrically connected to storage node electrode 5 by contact plug 7 are provided to storage node electrode 5. In addition, the cell transistor TEG having the above-described arrangement is formed based on the same steps as a transistor in the memory cell region by the DRAM (Dynamic Random Access Memory) manufacturing techniques.
Here, in the cell transistor TEG formed by the above-described structure, since storage node electrode 5 has a thick film stacked structure with the doped polysilicon deposited to the thickness of 500 nm as shown in FIG. 23, when a contact hole 6a for providing a tungsten plug 7 is formed in interlayer film 6 by etching, contact hole 6a never penetrates through storage node electrode 5. As a result, the reliable formation of interconnections on the storage node side of cell transistor TEG can be ensured.
As described above, when manufacturing the cell transistor TEG formed based on the same steps as the transistor of the memory cell region by DRAM manufacturing techniques, since the film thickness of doped polysilicon that forms storage node electrode 5 is as thick as 500 nm in a conventional thick film stacked capacitor structure, contact hole 6a formed by etching does not penetrate through storage node electrode 5, and thus, tungsten plug 7 for cell transistor TEG and aluminum interconnection 8 can be provided.
In order to produce a capacitor with a large capacity, however, when a cylindrical structure is employed as a storage node structure instead of the thick film stacked capacitor structure, the film thickness of doped polysilicon forming storage node electrode 5 is reduced to 50 nm, which is approximately one-tenth of the thickness found in the conventional structure. As a result, a reliable contact in the storage node side cannot be ensured when the interconnection structure for the conventional cell transistor TEG is employed.
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof which provide a structure of an interconnection drawn from an electrode of a semiconductor device that allows the production of a cell transistor TEG capable of performing a stable and reliable measurement of the characteristics of a cell transistor.
According to one aspect of the semiconductor device based on the present invention, the semiconductor device provided with a cell transistor test element group TEG having a cell transistor region and an interconnection region has a connecting structure for electrically connecting the interconnection region with a cylindrical storage node electrode provided in the cell transistor region, where the cell transistor region and the interconnection region are disposed in different regions in plan view, and the connecting structure has a groove-shape drawn-out electrode along a sidewall of a groove portion.
By employing the groove-shape drawn-out electrode connected to the cylindrical storage node electrode, the groove-shape electrode is drawn out to the vicinity of the interconnection region. Thus, even in the case of the cell transistor test element group of a cell transistor using the cylindrical capacitor structure, a reliable contact between the cylindrical storage node electrode and the interconnection region can be ensured via the groove-shape electrode which is in contact with the cylindrical storage node electrode. As a result, the test element group can be used to measure the transistor characteristics in a stable manner.
In addition, in the above invention, the connecting structure preferably includes an extended pad electrode portion extending from the groove-shape drawn-out electrode above the groove portion, and a contact plug which penetrates through the extended pad electrode portion and which connects the extended pad electrode portion with the interconnection region provided in a layer above the groove-shape drawn-out electrode.
With this arrangement, a sidewall of the contact plug is reliably connected with the extended pad electrode portion, and the reliable electrical connection can be established between the groove-shape electrode (which is connected to the extended pad electrode portion) with which the cylindrical storage node electrode makes contact and the interconnection region (which is connected to the contact plug). As a result, the measurement of the transistor characteristics can be performed in a stable manner.
Moreover, in the above invention, the connecting structure preferably includes a conductive layer disposed in a layer below the groove-shape drawn-out electrode, a first contact plug for connecting the groove-shape drawn-out electrode and the conductive layer, an interconnection layer provided in a layer above the conductive layer and below the groove-shape drawn-out electrode, a second contact plug for connecting the interconnection layer and the conductive layer, and a third contact plug for connecting the interconnection layer and the interconnection region. Furthermore, the conductive layer preferably is a gate electrode layer or a landing pad.
Moreover, in the above invention, the connecting structure preferably includes an interconnection layer provided in a layer below the groove-shape drawn-out electrode, a first contact plug for connecting the groove-shape drawn-out electrode and the interconnection layer, and a second contact plug for connecting the interconnection layer with the interconnection region.
Furthermore, in the above invention, the connecting structure preferably includes an interconnection layer provided in a layer below the groove-shape drawn-out electrode and having a lower end portion directly connected to the groove-shape drawn-out electrode, and a contact plug for connecting the interconnection layer with the interconnection region. The interconnection region preferably is an aluminum interconnection layer.
According to another aspect of the semiconductor device based on the present invention, the present semiconductor device is provided with a cell transistor test element group TEG having a cell transistor region and an interconnection region, where the cell transistor region and the interconnection region are disposed in a substantially same region in plan view, and the connecting structure has a contact plug connecting the cylindrical storage node electrode with the interconnection region. The interconnection region preferably is a bit line interconnection layer.
By employing each of the above-described arrangements, reliable electrical contact can be ensured between the cylindrical storage node electrode and the interconnection region so that the measurement of the transistor characteristics can be performed in a stable manner.
According to a further aspect of the semiconductor device based on the present invention, the present semiconductor device is provided with a cell transistor test element group having a cell transistor region and an interconnection region, where the cell transistor region includes a substantially elongate active region, a gate electrode provided in a direction perpendicular to the longitudinal direction of the active region, a bit line that extends in the longitudinal direction of the active region above the gate electrode and that is provided such that it does not overlap the active region in plan view, a landing pad disposed below the interconnection region and connected to the active region, and a contact plug connecting the landing pad with the interconnection region.
According to the above-described arrangement, the electrical connection between the active region and the interconnection region can be ensured via the landing pad and the contact plug. As a result, the interconnection can be drawn out from the active region of the cell transistor so that the measurement of the transistor characteristics can be performed in a stable manner.
According to a still further aspect of the semiconductor device based on the present invention, the present semiconductor device preferably is provided with a cell transistor test element group having a cell transistor region and an interconnection region, where the cell transistor region includes a substantially elongate active region, a gate electrode provided in a direction perpendicular to a longitudinal direction of the active region, and a bit line that extends in the longitudinal direction of the active region above the gate electrode and that is provided such that it does not overlap the active region in plan view, and the interconnection region includes a contact plug that is provided above the cell transistor region with an interlayer film provided therebetween and that connects the interconnection region with the active region. In the above-described invention, the contact plug preferably has a two-part structure.
According to the above-described arrangement, the electrical connection between the active region and the interconnection region can be ensured by the contact plug. As a result, the interconnection can be drawn out from the active region of the cell transistor so that the measurement of the transistor characteristics can be performed in a stable manner.
According to one aspect of the method of manufacturing a semiconductor device based on the present invention, the method of manufacturing a semiconductor device provided with a cell transistor test element group having a cell transistor region and an interconnection region includes the steps of forming the cell transistor region provided with a cylindrical storage node electrode, forming a contact plug connected to the cylindrical storage node electrode, and forming an interconnection region connected to the contact plug.
By producing a semiconductor device from the above steps, the cylindrical storage node electrode and the interconnection region can be reliably connected by the contact plug. As a result, the interconnection can be drawn out from the cylindrical storage node electrode so that the measurement of the transistor characteristics can be performed in a stable manner.
According to another aspect of the method of manufacturing a semiconductor device based on the present invention, the method of manufacturing a semiconductor device provided with a cell transistor test element group having a cell transistor region and an interconnection region includes the steps of forming the cell transistor region including a substantially elongate active region, a gate electrode provided in a direction perpendicular to a longitudinal direction of the active region, and a bit line that extends in the longitudinal direction of the active region above the gate electrode and that is provided such that it does not overlap the active region in plan view; forming an interlayer film covering the cell transistor region; forming a first contact plug and a second contact plug buried in the interlayer film and connected to the active region; and forming the interconnection region contacting the second contact plug on an upper surface of the interlayer film.
By producing a semiconductor device from the above steps, the interconnection region and the active region can be reliably connected by the first and second contact plugs. As a result, the interconnection can be drawn out from the active region so that the measurement of the transistor characteristics can be performed in a stable manner.